TSMC's Cross‑Node Utilization and Trucking Boost AI Chip Supply

TSMC is currently engaged in a significant expansion of its manufacturing capabilities, with new fabs under construction across Taiwan. This includes Fab 20 in Baoshan, Hsinchu, with four phases (one completed); Fab 22 in Nanzih, Kaohsiung, with five planned phases (one completed, two with shells up and equipment moving in); and Fab 25 in Taitung, which is currently just a dirt site but is expected to progress rapidly. Additionally, massive advanced packaging fabs are being built, such as AP7 in Chiayi, next to the Southern Branch of the National Palace Museum.

TSMC has allocated over $60 billion in capital expenditure for 2026 to support these new fabs. However, the insatiable demand for AI chips, particularly from customers like Nvidia, presents a challenge. As noted by TSMC's top management, including CEO C.C. Wei, capital expenditure spent in 2026 will not translate into market availability until 2028, or possibly a bit earlier. This raises questions about whether the AI boom will face a pause.

Cross-Node Utilization: TSMC's Solution

TSMC has a strategy to address this gap: cross-node utilization. This involves leveraging the iterative nature of semiconductor manufacturing processes and the significant overlap in tools and processes between different nodes.

The Iterative Nature of Process Nodes

A key, often underrated, aspect of semiconductor manufacturing is that everything in a process node is iterative. While logic process node names can be misleading, the underlying technology evolves incrementally.

Advanced nodes are developed in partnership with customers. TSMC's R&D team compiles various technologies, which are then curated and packaged for specific customers, leading to highly customized nodes. This customization explains why TSMC's node roadmap appears complex, with transitions like N3 to N3E, N3P, N3X, N3C, and N2 splintering into N2P, N2X, and A16, rather than a simple N3 to N2 transition.

Once a node is in the fab, the manufacturing team continuously works to improve yield through experiments. Over months, yields can improve significantly, often reaching the mid-80s percent. These improvements can be substantial enough for managers to repackage and rebrand a node (e.g., N6 from N7) or reserve improvements for future nodes.

Essentially, a process node involves a collection of tools in a fab, with wafers moving between these tools according to a preset recipe.

TSMC's Traditional Fab Strategy vs. Intel's

TSMC's general approach has been to build entirely new fabs or fab phases for brand new process nodes. For instance, Fab 15 in Taichung was built for the N7 node, and Fab 18 in Tainan was built for the N5 node.

This contrasts with companies like Intel, which tend to build one large fab shell and then fill it or upgrade tools over time as products advance. The reasons for this difference are varied: * Intel, as an integrated device manufacturer, doesn't need to produce older nodes for external clients in the same way TSMC does. * TSMC's fabs cater to clients who might purchase the same chips for extended periods. * Accounting plays a role: depreciation is a significant cost for a fab. After 5-7 years, a fab can become fully depreciated, making its revenue, net of operating costs, largely profit.

The Challenge of Stranded Fabs

A challenge with TSMC's traditional model arises when major customers migrate to newer nodes. For example, if a large customer like Apple shifts from N7 to N5, the production volume leaves the N7 fab in Taichung, creating an "Apple-sized hole" in its production. This can lead to a fab being underutilized or "stranded."

Currently, N2 is too new and immature for most customers, though adoption is expected soon. N3 is the current sweet spot, used by major customers like Nvidia for its latest Vera Rubin platform. N4 is older but still leading-edge and suitable for high-performance compute.

However, N7/N6, being almost 10 years old, is in a difficult position. It's too far from the leading edge for advanced applications but too expensive and complex for trailing-edge customers who prefer cheaper, more mature nodes like 28 nanometers. This leaves N7 in a "no man's land." If utilization drops too low (e.g., 60-70%), a fab can lose money and become a stranded investment. TSMC experienced this in early 2023 when N7 fabs in Taichung dropped below 70% utilization due to the post-COVID chip bust.

Leveraging Layer Overlap

Semiconductors are built in layers. While critical transistor layers differ significantly between nodes, many other layers, particularly the higher metal layers (interconnects), can be similar or even identical across different nodes (e.g., N16, N10, N7, N6, N5, N4, N3). This is why older DUV machines are still used for these higher layers.

For over a decade, TSMC has exploited this layer overlap to prevent fab strandings. * In 2015, then co-CEO Mark Liu noted a 95% tool overlap between 20-nanometer and 16-nanometer nodes, allowing capacity conversion without building new fabs. * In 2018, co-CEO C.C. Wei stated a 90% tool overlap between N10, N7, and N7 Plus (a modified N7 with EUV, made for Huawei). * CFO Laura Ho later confirmed over 90% tool overlap from N7 to N5.

This strategy allows TSMC to manage N10, N7, and N5 as a single, massive pool of capacity, upgrading fabs to newer nodes as customers progress, thus avoiding stranded investments and saving on capital expenditure.

The AI Boom and Cross-Node Utilization

The current AI boom presents an unprecedented demand for advanced capacity, especially N3. Fortunately, N3 has a 90% tool overlap with N5. In 2024, TSMC announced it was converting N5 capacity to N3, accepting a gross margin hit in the process.

Initially, converting N7 capacity to N3 was deemed much harder due to less overlap and the physical distance between N7 fabs (Taichung) and N5/N3 fabs (Tainan's Fab 18, which has a massive wafer bridge connecting its phases).

However, by early 2025, C.C. Wei revealed a solution for cross-utilizing N7 and N5 nodes, despite the 100-mile distance between their respective fabs.

The Role of Trucks in Cross-Node Utilization

TSMC's solution involves massively expanding its trucking service. After wafers complete critical front-end processing in Tainan (for N3 or N5), these unfinished wafers are loaded into ordinary trucks and transported 100 miles to underutilized N7/N6 fabs in Taichung, where the remaining layers are completed. This allows the Tainan fabs to focus solely on critical work, maximizing their capacity.

TSMC already uses trucks to transport finished wafers from front-end fabs to advanced packaging fabs (e.g., in Miaoli or Jiayi) for processes like CoWoS or InFO. These are semi-customized trucks carrying FOUPs (Front Opening Unified Pods) containing wafers worth tens of millions of dollars. TSMC's ESG site even details efforts to improve logistics and working conditions for these truck drivers.

These trucks, possibly bearing a TSMC logo or a derivative, are the low-tech backbone of this high-tech infrastructure. This cross-utilization is likely a temporary measure while TSMC converts N5 capacity to N3 by installing new tools. If N3 demand remains strong, TSMC may eventually convert N7/N6 capacity as well.

This strategy highlights TSMC's unique ability to leverage its existing infrastructure and the iterative nature of semiconductor manufacturing to rapidly scale production volumes, a capability unmatched by other companies, particularly within the concentrated ecosystem of Taiwan.