3D DRAM Stacking Challenges and Emerging Solutions Explained

DRAM (Dynamic Random-Access Memory) has reached a plateau in lateral scaling, meaning significant gains in bit density now primarily depend on vertical stacking. While 3D NAND revolutionized memory scaling by stacking cells, applying the same principle to DRAM, specifically stacking cells rather than entire dies, presents unique challenges.

Beginnings of DRAM

A DRAM cell fundamentally consists of one transistor and one storage capacitor. The transistor acts as a gate, controlling the flow of current to and from the capacitor, which temporarily stores an electrical charge. This charge needs constant refreshing due to its short retention time.

DRAM cells are connected by a wordline and a bitline. The wordline activates the transistor's gate, while the bitline serves as the path for charge to enter or exit the capacitor via the transistor.

Increasing bit density traditionally involves shrinking the DRAM cell size. However, a smaller capacitor leads to reduced capacitance, making it harder to detect voltage changes on the bitline and shortening the charge retention time. This necessitates more frequent refreshes, increasing power consumption. Overcoming these technical hurdles while maintaining low production costs is crucial, as DRAM is a commodity with fluctuating market prices.

Eras of Scaling

DRAM scaling has seen several key technological advancements:

• 3D Capacitors (2000s): Planar capacitors were replaced by 3D structures:
  • Trench Capacitors: Etched into the silicon substrate, with the transistor built on top.
  • Stacked Capacitors: Built on top of their access transistors. While trench capacitors were initially popular, stacked capacitors became dominant after the adoption of heat-sensitive High-K metal dielectrics, which require the transistor to be built first.
• EUV Lithography: Enables printing smaller features and new structures like honeycomb or staggered arrays, reducing mask steps and costs.
• 4F2 Cell Design: Since 2007, DRAM cells primarily used a 6F2 layout (2F by 3F, where F is the minimum feature size). The upcoming 4F2 design (2F by 2F) offers a 33% shrink by placing a vertical gate access transistor directly beneath the capacitor and reducing bitline and wordline sizes.
  • Challenges with 4F2: Vertical gate transistors in 4F2 designs are susceptible to the "floating body effect," where charge accumulation can lead to accidental voltage and data leakage from the capacitor.

Despite these advancements, physical shrinking is becoming increasingly difficult. Lam Research predicts that density gains will cease around 2029-2030 when the area per bit reaches approximately 1000 square nanometers (32x32 nm). This looming limit has spurred serious consideration of 3D NAND-like DRAM stacking.

Remembering 3D NAND

While High Bandwidth Memory (HBM) already employs a form of 3D DRAM by stacking dies using advanced packaging techniques like wafer bonding, this differs from how 3D NAND achieves its density.

3D NAND overcame planar scaling limitations by "stepping back" to larger, more reliable flash memory cells and compensating with massive vertical stacks. This is achieved by:

1. Depositing dozens of alternating dielectric layers.
2. Patterning and punching deep channels through these layers.
3. Producing charge traps within the channels, with each layer forming a memory cell.

The critical lithography and etching steps are performed once, regardless of the number of layers, enabling stacks of 100, 200, or even 300 layers.

Stacked Horizontal Capacitors

The primary challenge for post-4F2 3D DRAM lies in redesigning the capacitor. Traditional vertical cylindrical capacitors are too "thick" to stack effectively in large numbers.

One intuitive idea is to orient these capacitors horizontally. However, this presents significant manufacturing difficulties:

• Lateral Etching and Deposition: Existing techniques are optimized for vertical etching and deposition. Controlling reactants for lateral etching and uniformly filling horizontal holes is complex.
• Capacitor Length: Current DRAM capacitors can be 1-3 micrometers deep but only 20-30 nanometers wide. Achieving 3 micrometers of lateral etching is currently impossible, meaning horizontal capacitors would be shorter and less effective.
• Interconnections: Connecting wordlines and bitlines in a dense, sideways arrangement is extremely challenging.

Benjamin Vincent of Lam Research, using a process simulator, proposed an alternative architecture:

• Short and Wide Capacitors: Redesigning capacitors to be short and wide, maintaining capacitance through increased surface area.
• Bitline Relocation: Moving bitlines to the end of the sheet structure to create a shared "bitline trunk" between opposing sheets.
• Gate-All-Around Transistors: Utilizing advanced gate-all-around transistors for better current control and gating performance.

This architecture resembles a "Lego pine tree" or a staggered building structure.

Vertical Bitline (VBL) vs. Horizontal Bitline (HBL)

Several 3D DRAM designs feature short, wide horizontal capacitors. A key differentiator among these designs is the placement of bitlines and wordlines:

• Vertical Bitline (VBL): The bitline runs vertically through multiple layers, while the wordline remains horizontal within each layer.
• Vertical Wordline (VWL): The wordline runs vertically, with a horizontal bitline.

Industry consensus suggests that Vertical Bitline designs hold more promise due to a smaller physical footprint and direct connection to peripheral CMOS circuits, though full production challenges remain.

Industry Developments

DRAM manufacturers are actively pursuing these 3D DRAM variants:

• Micron: Has been patenting horizontally oriented DRAM cells for over a decade, focusing on cost optimization and ensuring transistor and capacitor performance in stacked configurations. While rumors circulate, Micron has not officially announced breakthroughs.
• Samsung: In May 2024, a Samsung EVP reported completing a 16-stack 3D DRAM using a "Vertically Stacked Cell Array Transistor" (VS-CAT) style, later rebranded as "Vertically Stacked DRAM" (VS-DRAM). This approach reportedly uses wafer bonding to connect memory cell wafers with peripheral CMOS support circuits.
• CXMT (China): In March 2026, CXMT published a paper on a five-layer 3D DRAM using a vertical wordline design. They also hinted at a 64-layer test vehicle for process testing.

Capacitor-less 3D DRAM

Given the challenges with capacitors, some research explores capacitor-less 3D DRAM. While concepts like floating body DRAM and A2RAM have existed, their performance and robustness were limited by leaky silicon transistors.

A significant breakthrough emerged in 2020 with the proposal of a capacitor-less design using indium-gallium-zinc oxide (IGZO).

IGZO and IMEC

IGZO, discovered in 2004 and commercialized by Sharp for flexible displays, is known for its amorphous structure, transparency, and critically, ultra-low leakage when off.

In 2020, an IMEC team led by Attilio Belmonte proposed the IGZO 2T0C DRAM cell, replacing the traditional 1T1C (one transistor, one capacitor) with two thin-film IGZO transistors. This design is a variation of older 2-transistor gain cell memory, where one transistor's gate acts as the capacitor.

• Operation: One transistor is for writing, the other for reading. When the write transistor activates, charge flows into the read transistor's gate, stored via parasitic capacitance. Reading involves a small current through the read transistor; the stored charge alters its conductivity, indicating a '1' or '0'. This read operation is non-destructive, unlike traditional DRAM.
• Advantages: IGZO's high bandgap and near-zero leakage make this design feasible, offering significantly longer data retention times (up to 400 seconds, 1000 times longer than regular DRAM). The transistor can also scale down to 14 nanometers without losing retention.

IGZO Shortfalls

Despite its promise, IGZO 3D DRAM faces challenges:

• Cell Size: Requires numerous contacts and interconnects, potentially leading to larger cells (e.g., 9F2).
• Stacking Complexity: While IGZO films are easy to deposit, the non-flat cell structure with irregular bumps from interconnects can complicate large stack construction.
• Reliability: The small, fragile capacitor/gate in 2T0C cells is susceptible to manufacturing defects and external effects that can degrade transistor performance over time.
• Positive Bias Temperature Instability (PBTI): A constant electric field at elevated temperatures can trap electrons in the gate oxide, shifting the transistor's threshold voltage and affecting bit readability. This issue is exacerbated by mechanical stress and higher temperatures in 3D stacks.

Nevertheless, the IMEC paper has spurred extensive research, and IGZO is now considered a serious contender for future DRAM roadmaps, alongside other concepts like thyristor-based memory.

Conclusion

As true 3D DRAM cell stacking is not yet production-ready, the current industry trend involves stacking more DRAM dies using advanced packaging techniques like HBM.

Bringing 3D NAND's scalability to DRAM would be revolutionary, but it's a complex endeavor. Unlike NAND, which focuses on bulk, non-volatile storage, DRAM requires fast random access, unlimited rewrite cycles without wear, and low leakage, in addition to high density.

Despite the challenges, significant progress is being made, and true 3D DRAM is anticipated to emerge by the end of the decade.